1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a structure of a semiconductor device having a thin film transistor.
2. Description of the Background Art
In recent years, for meeting a demand for shrinking the size of a semiconductor-device, development on a thin film transistor (hereinafter referred to as TFT) to be formed as a field effect transistor by forming a semiconductor thin film on an insulator substrate and providing a channel in the semiconductor thin film has been under way.
A description of a structure of the TFT follows in conjunction with the accompanying drawings.
Referring to FIG. 48, a gate electrode 2 of polysilicon is formed on an interlayer insulating film 1 formed on a bulk transistor (not shown). A gate oxide film 6 is formed along the top flat portion and sidewalls of gate electrode 2. A semiconductor layer 7 is formed along gate oxide film 6. Formed at a position of semiconductor layer 7 opposite to gate electrode 2 is a channel region 7a. Source/drain regions 7b, 7c are formed at positions having channel region 7a therebetween.
A description of a manufacturing process of a TFT having the above-stated structure follows in conjunction with FIGS. 49-55.
Referring to FIG. 49, an interlayer insulating film 1 is formed as thick as 1500 nm on a bulk transistor (not shown) by thermal chemical vapor deposition. A polysilicon layer 2 to be the gate electrode 2 of the TFT is deposited as thick as 200 nm on interlayer insulating film 1 by means of thermal chemical vapor deposition.
Referring to FIG. 50, a resist film 4 having a prescribed form is formed on the surface of polysilicon layer 2 by a photolithography technique. Referring to FIG. 51, using resist film 4 as mask, polysilicon layer 2 is subjected to anisotropic reactive ion etching to form gate electrode 2.
Referring to FIG. 52, a resist film 4 is etched away. Referring to FIG. 53, an oxide film 6 for forming a gate oxide film having a thickness of 50 nm is formed on the surfaces of gate electrode 2 and interlayer insulating film 1 by thermal CVD. A polysilicon layer 7 to form the semiconductor layer of the TFT is deposited as thick as 50 nm on oxide film 6 by thermal chemical vapor deposition.
Referring to FIG. 54, a resist film 8 is formed on the surface of polysilicon layer 7. Resist film 8 is patterned into a prescribed form by means of a photolithography technique or the like. Using resist film 8 as mask, an impurity, for example, 1.times.10.sup.15 (cm.sup.-2) of boron for forming source/drain regions is implanted into polysilicon layer 7.
Referring to FIG. 55, resist film 8 is etched away. Thus formed is the TFT having channel region 7a in the region of polysilicon layer 7 opposite to the gate electrode 2 and source/drain regions 7b, 7c at the positions having channel region 7a therebetween.
The TFT having the structure described above, however, suffers from the following disadvantage. Referring to FIG. 55, gate electrode 2 is formed by subjecting the polysilicon layer to anisotropic reactive iron etching. Gate electrode 2 therefore takes a substantially rectangular form. Thus, with gate electrode 2 having a rectangular form, substantially orthogonal edges 9, 9 are produced in oxide film 6 and polysilicon layer 7 formed along gate electrode 2. Electric fields are likely to concentrate on these edges 9, 9 resulting in hot carriers or the like. The hot carriers enter into gate oxide film 6, thus deteriorating the insulation of gate oxide film 6.